(1) Field of the Invention
The present invention relates to the field of fabricating integrated circuits, and particularly the field of via or contact etching of insulating films formed in semiconductor devices.
(2) Prior Art
In the fabrication of integrated circuits, it is often desired to etch certain areas of a film formed in a semiconductor substrate used as an insulating layer between the gate regions of semiconductor devices and the interconnects formed above these regions. Via or contact etching of the film is performed to create contact openings in the insulating layer between the interconnects and the source and drain regions in the substrate. In the prior art, this has been most readily accomplished by reactive ion etching of a silicon oxide film used as the insulating film.
In the formation of contacts in a semiconductor substrate, a silicon oxide film is deposited over the gate, source and drain regions of the device. The film is then coated with a layer of an organic photoresist, with openings formed in the photoresist to expose selected areas of the underlying silicon oxide film. The device is next placed in an etch chamber of a reactive ion etch system to etch the exposed areas of the silicon oxide film.
The chamber, which is a controlled environment, includes means for introducing gas to the chamber and electrodes for producing plasma from the gas. Typically, a fluorine-oxygen gas mixture or chemistry is used for the etching of silicon oxide films. The gas is introduced to the chamber and RF energy is applied to produce the plasma. Etching takes place until the RF energy is removed, with the timing of the process, pressure, RF energy and flow rate controlling the depth of etching.
A significant drawback in the conventional methods for contact etching of the insulating film is the damage caused to the gate oxide and the resulting accumulation of charge at the interface between the gate and the silicon oxide film. A substantial amount of gate charging results during the etch process by the accumulation of charge in "traps" associated with defects in the silicon oxide film, such as impurities and broken bonds. When a considerable amount of gate charging occurs in a particular etch, the threshold voltage of the gate shifts, thereby changing the minimum bias of the gate, and in some cases, leading to complete breakdown of the gate oxide.
The problem of gate charging is further worsened by the fact that the accumulation of charge is cumulative throughout the entire manufacturing process of semiconductor devices. Since gate charging increases as the sequential steps of the manufacturing process are performed, additional steps have been implemented throughout the process to prevent or cure the damage. Clearly, the occurrence of gate charging results in a significant increase in cost and a reduced yield in the over-all manufacture of semiconductor devices.
In response to this problem, several prior art methods have been devised in an attempt to prevent or cure the resulting gate oxide damage. A first prior art method employs the use of high temperature annealing steps in the manufacturing process to cure the damage after it has occurred by tying up any existing broken bonds. A second prior art method comprises the addition of various insulating films on the backside of the substrate through well-known deposition techniques to prevent the accumulation of charge through contact with potential sources of charge. A third prior art method consists of re-engineering the entire contact etch by varying the variables and chemistry of the particular etch. This re-engineering may require new process gasses and/or new equipment to obtain the proper etch in which gate charging is minimized.
There are several disadvantages in the prevention and/or cure of the gate oxide damage by the prior art methods. In the first method, the addition of extra annealing steps increases both the manufacturing cost and the cycle time for completing a batch. There are also process integration issues with this cure due to the fact that the high temperature requirements cause greater diffusion of the implanted source and drain regions, thereby limiting the high temperature steps that may be used later in the process. In addition, the gate oxide may be completely destroyed, in which case it is not possible to use this approach. With respect to the second method, the growth or deposition of a backside insulator requires an extra step in the manufacturing process, which therefore increases the cost and reduces the batch yield. There are also similar integration issues as with the first method due to the fact that the addition of a back-side insulator will alter several of the steps in the manufacturing process, especially those which require the wafer to be thermally treated. In the third method, the complete re-engineering of the etched gate is a very time consuming process which similarly increases cost and significantly affects the time it takes to qualify the batch before it can reach the market. In addition, the gate oxide damage is usually not identified until late in the manufacturing development cycle, thereby preventing adjustment of the etch process at such a late time.
Therefore, it is an object of the present invention to provide a method for the contact etching of silicon oxide films formed in semiconductor devices using a reactive ion etch system to prevent damage to the gate oxide, thereby minimizing charging of the semiconductor device.
It is a further object of the present invention to provide a method for the etching of insulating films using an improved fluorine/oxygen gas chemistry in a dry etch system to obtain a more uniform etch and prevent gate oxide damage without significantly affecting the other etch characteristics of the etch process.
Another object of the present invention is to avoid the costly and time consuming prior art methods for preventing and curing gate oxide damage.